74573 Octal Transparent Latch with TRI-STATE Outputs

Overview

The 74573 (also designated as 'LS573) is a high-speed octal transparent latch designed for bus-organized systems. This component features eight latches with TRI-STATE outputs for bus interfacing applications. The device is functionally identical to the 'LS373 but features an improved pinout arrangement with inputs and outputs on opposite sides of the package for easier printed circuit board layout.

The 74573 is particularly useful as an input or output port for microprocessor systems, providing temporary storage for data being transferred between the microprocessor and peripheral devices. The TRI-STATE outputs allow connection to a common bus while preventing bus contention.

Key Features

• High-speed octal transparent latch with 3-state outputs
• Inputs and outputs on opposite sides of package for improved PCB layout
• Buffered common Latch Enable (LE) and Output Enable (OE) inputs
• Input clamp diodes limit high-speed termination effects
• Fully compatible with TTL and CMOS logic levels
• TRI-STATE outputs for bus-oriented applications
• Functionally identical to 'LS373 with improved pinout
• Available in multiple package options including DIP and SOIC

Applications

The 74573 finds use in numerous digital systems applications including:

• Microprocessor input/output ports
• Bus interface units
• Data buffering and temporary storage
• Memory address latching
• Data routing and distribution systems
• Parallel-to-serial conversion systems
• Industrial control systems
• Communication equipment

Electrical Characteristics

Absolute Maximum Ratings

• Supply Voltage (VCC): 7V
• Input Voltage (VIN): 7V
• Output Voltage (VOUT): 5.5V
• Operating Free Air Temperature Range: 0°C to +70°C
• Storage Temperature Range: -65°C to +150°C

Recommended Operating Conditions

• Supply Voltage (VCC): 4.75V to 5.25V
• High-Level Input Voltage (VIH): 2V min
• Low-Level Input Voltage (VIL): 0.8V max
• Operating Temperature (TA): 0°C to +70°C

DC Characteristics

• High-Level Output Voltage (VOH): 2.7V min @ IOH = -400μA
• Low-Level Output Voltage (VOL): 0.5V max @ IOL = 8mA
• Input Clamp Voltage (VIK): -1.5V max @ IIK = -18mA
• High-Level Input Current (IIH): 20μA max @ VIN = 2.7V
• Low-Level Input Current (IIL): -0.4mA max @ VIN = 0.4V
• Output Short Circuit Current (IOS): -30mA to 60mA
• Supply Current (ICC): 24mA max

AC Characteristics

• Propagation Delay Time (tPLH, tPHL): 15ns max
• Output Enable Time (tPZH): 25ns max
• Output Disable Time (tPHZ): 20ns max
• Setup Time (tSU): 20ns min
• Hold Time (tH): 5ns min

Package Information

Available Packages

• DM74LS573N: 20-pin Plastic Dual-In-Line Package (PDIP), NS Package Number N20A
• DM74LS573WM: 20-pin Small Outline Integrated Circuit (SOIC), NS Package Number M20B

Pin Configuration

The 74573 features the following pinout:

• Pin 1: Output Enable (OE) - Active LOW
• Pin 2: Output O0
• Pin 3: Output O1
• Pin 4: Output O2
• Pin 5: Output O3
• Pin 6: Output O4
• Pin 7: Output O5
• Pin 8: Output O6
• Pin 9: Output O7
• Pin 10: Ground (GND)
• Pin 11: Latch Enable (LE) - Active HIGH
• Pin 12: Data Input D7
• Pin 13: Data Input D6
• Pin 14: Data Input D5
• Pin 15: Data Input D4
• Pin 16: Data Input D3
• Pin 17: Data Input D2
• Pin 18: Data Input D1
• Pin 19: Data Input D0
• Pin 20: VCC (+5V)

Functional Description

The 74573 octal transparent latch operates as follows:

Latch Operation

When the Latch Enable (LE) input is HIGH, the Q outputs follow the data (D) inputs. When LE goes LOW, the data present at the D inputs at that time is latched and held at the outputs until LE goes HIGH again.

TRI-STATE Operation

The Output Enable (OE) input controls the TRI-STATE outputs. When OE is LOW, the outputs are active. When OE is HIGH, the outputs are in a high-impedance state, effectively disconnecting the latch from the bus.

Function Table

Design Considerations

When using the 74573 in system designs, consider the following:

• Proper decoupling capacitors (0.1μF) should be placed near the VCC and GND pins
• Unused inputs should be tied to either HIGH or LOW through a resistor
• The device should not be operated outside its absolute maximum ratings
• When driving heavy loads, consider the maximum output current specifications
• For high-speed designs, transmission line effects should be considered