Keep The Ramp right

Description: If the ramp driving your PWM-based controller is not linear, monotonic, or is simply noisy, your DC/DC converter will not perform optimally. It is essential to understand how to achieve the best performance from your system. A typical DC/DC power system relies on the slope of a ramp to establish the duty cycle of a pulse width modulation (PWM) controller. This applies to both voltage-mode controllers, which utilize a separately generated ramp for pulse width setting, and current-mode controllers, which employ a ramp generated by a current sensor monitoring the current in the switching element. A typical block diagram of a voltage-mode power controller, such as the UC2823, is shown in Figure 1. Figure 2 presents a simplified schematic of the control circuit in a forward converter topology. When the MOSFET power switch is activated by the control circuit signal OUT, voltage VIN is applied across the primary winding of transformer T1, resulting in voltage VTOUT appearing at the secondary of T1. This voltage is directed to output inductor LOUT through diode D1, which is greater than the output voltage VOUT, causing a buildup of current in LOUT. When the power MOSFET turns off, the voltage at the input of LOUT drops to zero; however, current continues to flow through diode D2 and LOUT, decreasing linearly. For this analysis, the design parameters of the forward converter are set for an input-voltage range from 36 to 57 volts and an output of 100 watts. The output voltage is established at 5 volts, and the switching frequency is set at 100 kHz, with a target to minimize output ripple to no more than 50 mV. Inductor LOUT is sized for a peak-to-peak ripple current of 20 percent. The output capacitor is selected such that half of the output ripple is influenced by the capacitance, and half is affected by the equivalent series resistance (ESR) of the capacitor. The design calculations yield a transformer turns ratio of 11 to 2, an output inductor of 4.6 microhenries, and an output capacitance of 400 microfarads with a maximum ESR of 6.25 milliohms. This information allows for the calculation of the gain of the output filter as a function of frequency (Figure 3). The control-to-output voltage gain of the power stage can be investigated using the UC2823's datasheet, which indicates that the ramp on the Ct pin (oscillator) has a typical valley voltage of 1.0 volt and a peak voltage of 2.8 volts. At maximum input voltage, the calculated duty cycle is 0.367, while at minimum input voltage, it is 0.859. When the circuit is in regulation, the ramp voltage switch point at maximum input voltage will be 1.66 volts, and at minimum input voltage, it will be 2.62 volts. The control-to-output gain at each of these input voltages and duty cycles can be determined by calculating the change in output voltage for a given change in COMP voltage of +100 millivolts and finding the new duty cycle. The corresponding change in output voltage can then be calculated for each condition, and the difference divided by 0.1 volt yields the DC control-to-output gain. The calculations result in a control-to-output gain of 7.576 at maximum input voltage and 5.596 at minimum input voltage. Figure 4 illustrates a diagram of a linear ramp and the four control (COMP) voltages for the duty cycle. The control voltages are arranged in pairs; each pair represents either a high or low input voltage (VIN minimum corresponds to V2, and VIN maximum corresponds to V1). The lower voltage in each pair indicates the control voltage required for a regulated output, while the upper line shows the addition of 100 mV to the control voltage.

In a PWM-based DC/DC converter, the ramp signal plays a crucial role in regulating output voltage by determining the duty cycle of the switching device. A linear and monotonic ramp signal ensures stable operation, minimizing output voltage fluctuations. Voltage-mode controllers utilize an externally generated ramp, while current-mode controllers derive their ramp from a current sensing mechanism. The forward converter topology, often employed in these systems, consists of a MOSFET switch, a transformer, diodes, and inductors, all working in tandem to convert input voltage to a desired output voltage efficiently.

The transformer in the forward converter is pivotal, as it steps down the voltage while providing isolation. The turns ratio is critical, affecting the output voltage and current. The output inductor plays a significant role in smoothing the output current, while the output capacitor, selected based on its capacitance and ESR, helps mitigate voltage ripple. The design parameters, including input voltage range, output power, and switching frequency, are essential for optimizing converter performance. The target output ripple voltage is a key design consideration, as excessive ripple can lead to instability in downstream circuits.

The control-to-output gain is a vital metric for assessing the performance of the converter. By analyzing the duty cycle across varying input voltages, one can determine how effectively the controller responds to changes in output voltage. The calculated gains provide insight into the dynamic behavior of the converter, ensuring that it can maintain regulation under different load conditions. Overall, careful consideration of the ramp signal characteristics, component selection, and feedback mechanisms are essential for achieving optimal performance in PWM-based DC/DC converters.If the ramp driving your PWM-based controller isn`t linear or monotonic, or just plain noisy, your DC/DC converter isn`t going to work up to its capabilities. Here`s what you need to know to get the best performance from your system. Today`s typical DC/DC power system relies on the slope of a ramp to set the duty cycle of a pulse width modulating(PWM) controller.

This is true for both voltage-mode controllers, which use a separately generated ramp for setting the pulse width; and current-mode controllers, which use a ramp generated by a current sensor monitoring the current in the switching element. Figure 1 shows a typical block diagram of a voltage-mode power controller, in this example the UC2823.

A simplified schematic of the control circuit in a forward converter topology is shown in Fig. 2. When the MOSFET power switch is turned on by the control circuit signal OUT, voltage VIN is applied across the primary winding of transformer T1. Thus voltage VTOUT appears at the secondary of T1. It`s applied to output inductor LOUT through D1. This voltage is greater than the voltage on the output, VOUT. As a result, there`s current buildup in LOUT. When the power MOSFET turns off, the voltage on at the input of LOUT drops to zero. However, current is drawn through diode D2 and continues to flow through LOUT, though it decreases in a linear manner.

For this analysis we set the design parameters of a forward converter for an input-voltage range from 36 to 57 volts, and an output of 100 watts. The output voltage is set at 5 volts, and the switching frequency is 100 kHz. We want to minimize the output ripple ”no more than 50 mV. We size inductor LOUT for a peak-to-peak ripple current of 20 percent. We select the output capacitor so that half the output ripple is a function of the capacitance, and half is a function of the equivalent series resistance (ESR) of the capacitor.

The calculations for this design yield a transformer turns ratio of 11 to 2, an output inductor of 4. 6 microhenries and an output capacitance of 400 microfarads with a maximum ESR of 6. 25 milliohms. From this information, we can calculate the gain of the output filter as a function of the frequency (Fig 3).

Next, investigate the control-to-output voltage gain of the power stage. To do this, we go to the UC2823`s datasheet, which indicates a ramp on the Ct pin (oscillator) has a typical valley voltage of 1. 0 volt and peak voltage of 2. 8 volts. At the maximum input voltage, the duty cycle is 0. 367 (calculated). At minimum input voltage, the duty cycle will be 0. 859. When the circuit is in regulation, the ramp voltage switch point at maximum input voltage will be 1. 66 volts, and 2. 62 volts at minimum input voltage. We can now determine the control-to-output gain at each of these input voltages and duty cycles by simply calculating the change in output voltage for the same input voltage from: We calculate the corresponding change in the output voltage of the converter by changing the voltage at COMP by +100 millivolts and finding the new duty cycle.

From this, we calculate the new output voltage for each condition using the above formula. Determine the difference in the output voltage and divide the difference by 0. 1 volt. This is the DC control-to-output gain. Running through the calculations, we get a control-to-output gain of 7. 576 at maximum input voltage. At minimum input voltage, we calculate the control-to-output gain as 5. 596. Figure 4 shows a diagram of a linear ramp and the four control (COMP) voltages for the duty cycle. The control voltages are arranged in sets of two; each set represents either a high or low input voltage (VIN minimum corresponds to V2, and VIN maximum corresponds to V1). The lower voltage in each voltage pair (V1 and V2) indicates the control voltage needed for a regulated output.

The upper line indicates we have added 100 mV to the control voltage. The actual chan