early philips colour tv

Description: A pair of thyristors in a controlled full-wave bridge configuration provides a 100Hz rectified supply. This is smoothed by an active smoothing circuit to give a DC supply of 1.56V. The thyristors only conduct for a short period when they are triggered in the latter half of each mains half-cycle. Stabilization of the DC output voltage against both mains voltage changes and load variations is achieved by controlling the conduction angle of the thyristors. The trigger pulses are produced by a silicon controlled switch with a phase control circuit that senses the mains input and the DC output voltages. At switch-on, the phase control circuit provides slow start-up. In addition to the normal CRT beam current limiter in the signal circuits, further protection is provided by reducing the power supply output voltage if the EHT current becomes excessive. A monostable gating circuit inhibits spurious thyristor triggering by spikes that may be present on the incoming mains supply. Over-voltage protection is incorporated. Two diodes A/B of the four-diode encapsulation D4005, along with the two thyristors SCR4018/20, form a controlled full-wave (100Hz) bridge rectifier circuit. Thyristor conduction, and therefore the power into the load, is controlled by changing the phase of the thyristor trigger pulses, and by this means, a stabilized DC output is obtained. All four diodes of D4005 form a second full-wave bridge rectifier to provide a separate 100Hz supply for the trigger pulse generator SCS4061. The input bridge circuit is such that the receiver chassis is floating at about half-mains potential irrespective of which way the mains connection is made. Two fuses FS1301/02 are fitted, so that, regardless of which mains input lead is live, there is protection for a short circuit between chassis and true earth during servicing. For reliability reasons, the mains input to the two thyristors is taken via paralleled plugs and sockets. VDR1307, in conjunction with the RF choke L1305 and capacitors C1304/06, suppresses incoming mains interference. The choke and capacitors are also partly responsible for preventing RF interference generated by the thyristors from entering the mains supply. In addition to this mains filter, the remaining interference resulting from the very rapid changes of peak current through the thyristors is eliminated by the two-chokes-on-one-core assembly L4009A/B. This choke is extremely important in order to avoid interference to MW and LW radio receivers. This is powered by the 100Hz unsmoothed rectified mains waveform from D4005. The waveform is attenuated and delayed by the phase shift network R4044/C4058, and the resultant rising voltage across C4058 is applied to the anode of the silicon controlled switch SCS4061. The SCS gate is fed from the same source via the attenuator R4059/60; C4062 is not large enough for protection purposes. An output pulse appears at the SCS cathode after the anode voltage has risen to meet the falling gate voltage. This is the source of trigger pulses for the two thyristors. The phase relationship of the anode and gate waveforms is such that a trigger pulse can only be produced during the back half of the positive input half-cycles. C4064 is for flashover protection. The timing of the trigger pulses is controlled by T4045 and then passed via the pulse inhibit gate T4072 and the trigger pulse amplifier T4068/77 to the thyristors. T4045 is placed in parallel with the trigger pulse generator charging capacitor C4058. The conduction of T4045 is determined by the rectified mains supply via R4059/53, and also by the DC stabilized output voltage fed back from C4029 via R4024/41/42, etc. The controlled conduction of T4045 restricts the charge entering C4058, thereby determining the amplitude of the SCS anode waveform. In this way, the transistor controls the phase of the trigger pulses which, in turn, vary the conduction periods of the thyristors.

The described circuit employs a pair of thyristors configured in a controlled full-wave bridge rectifier arrangement, effectively converting alternating current (AC) to direct current (DC) at a frequency of 100Hz. The design incorporates active smoothing to ensure a stable DC output of 1.56V, which is crucial for various electronic applications. The thyristors are triggered to conduct during the latter portion of each mains half-cycle, allowing for controlled power delivery to the load.

The stabilization of the DC output voltage is achieved through a method known as phase control, which involves adjusting the conduction angle of the thyristors based on variations in both mains voltage and load conditions. This is facilitated by a silicon controlled switch (SCS) that generates trigger pulses in response to the detected mains input and output voltages. A slow start-up feature is integrated into the phase control circuit to prevent sudden surges in current when the circuit is powered on.

Protection mechanisms are also in place to safeguard the circuit from potential faults. A current limiter is deployed in the CRT beam current signal circuits, and additional measures are incorporated to lower the output voltage if excessive EHT current is detected. A monostable gating circuit serves to block unwanted triggering of the thyristors due to electrical noise or spikes on the mains supply. Over-voltage protection is included to further enhance the circuit's reliability.

The rectifier circuit consists of two thyristors (SCR4018/20) and two diodes from the D4005 encapsulation, effectively forming a controlled full-wave bridge rectifier. The additional diodes from the D4005 package are utilized to create a separate supply for the trigger pulse generator, ensuring that the system operates efficiently without interference from the main power supply.

To maintain safety during servicing, two fuses (FS1301/02) are installed, providing protection against short circuits between the chassis and earth. The mains input is designed with paralleled plugs and sockets for added reliability. Various components, including a voltage-dependent resistor (VDR1307), RF choke (L1305), and capacitors (C1304/06), work in conjunction to suppress mains interference and mitigate the generation of RF noise by the thyristors.

The circuit also employs a two-choke-on-one-core assembly (L4009A/B) to eliminate residual interference caused by rapid current changes through the thyristors, which is critical for preventing disruptions to medium-wave (MW) and long-wave (LW) radio receivers. The trigger pulse generation process is carefully timed and controlled using transistors (T4045, T4072) and amplifiers (T4068/77), ensuring that trigger pulses are only produced during the appropriate phase of the input half-cycles.

Overall, this circuit design exemplifies a sophisticated approach to rectification and voltage stabilization, incorporating multiple safety and interference-reducing features to ensure reliable operation in various electronic applications.A pair of thyristors in a controlled full-wave bridge configuration provide a 100Hz rectified supply. This is smoothed by an active smoothing circuit to give a DC supply of 1. 56V. The thyristors only conduct for a short period when they are triggered in the latter half of each mains half-cycle.

Stabilisation of the DC output voltage against both m ains voltage changes and load variations is achieved by controlling the conduction angle of the thyristors. The trigger pulses are produced by a silicon controlled switch with a phase control circuit which senses the mains input and the DC output voltages.

At switch-on, the phase control circuit provides slow start-up. In addition to the normal CRT beam current limiter in the signal circuits, further protection is provided by reducing the power supply output voltage if the EHT current becomes excessive. A monostable gating circuit inhibits spurious thyristor triggering by spikes which may be present on the incoming mains supply.

Over-voltage protection is incorporated. Two diodes A/B of the four-diode encapsulation D4005 along with the two thyristors SCR4018/20 form a controlled full-wave (100Hz) bridge rectifier circuit. Thyristor conduction, and therefore the power into the load is controlled by changing the phase of the thyristor trigger pulses, and by this means a stabilised DC output is obtained.

All four diodes of D4005 form a second full-wave bridge rectifier to provide a separate 100Hz supply for the trigger pulse generator SCS4061. The input bridge circuit is such that the receiver chassis is floating at about half-mains potential irrespective of which way round the mains connection is made.

Two fuses FS1301/02 are fitted, so that, regardless of which mains input lead is live , there is protection for a short circuit between chassis and true earth during servicing. For reliability reasons, the mains input to the two thyristors is taken via paralleled plugs and sockets.

VDR1307 in conjunction with the RF choke L1305 and C1304/06 suppresses incoming mains interference. The choke and capacitors are also partly responsible for preventing RF interference generated by the thyristors from entering the mains supply. In addition to this mains filter, the remaining interference resulting from the very rapid changes of peak current through the thyristors is eliminated by the two-chokes-on-one-core assembly L4009A/B.

This choke is extremely important in order to avoid interference to MW and LW radio receivers. This is powered by the 100Hz unsmoothed rectified mains waveform from D4005. The waveform is attenuated and delayed by the phase shift network R4044/C4058, and the resultant rising voltage across C4058 is applied to the anode of the silicon controlled switch SCS4061. The SCS gate is fed from the same source via the attenuator R4059/60; C4062 is not large enough protection purposes.

An output pulse appears at the SCS cathode after the anode voltage has risen to meet the falling gate voltage. This is the source of trigger pulses for the two thyristors. The phase relationship of the anode and gate waveforms is such that a trigger pulse can only be produced during the back half of the positive input half-cycles.

C4064 is for flashover protection. The timing of the trigger pulses is controlled by T4045 and then passed via the pulse inhibit gate T4072 and the trigger pulse amplifier T4068/77 to the thyristors. T4045 is placed in parallel with the trigger pulse generator charging capacitor C4058. The conduction of T4045 is deter-mined by the rectified mains supply via R4059/53, and also by the DC stabilised output voltage fed back from C4029 via R4024/41 /42 etc.

The controlled conduction of T4045 restricts the charge entering C4058, thereby determining the amplitude of the SCS anode waveform. In this way the transistor controls the phase of the trigger pulses which, in turn, vary the conduction periods of the thyristors, a