Sample and hold

Description: The JFETs, Q1 and Q2, provide complete buffering to C1, the sample and hold capacitor. During the sample phase, Q1 is activated, establishing a low-resistance path (rds(on)) for charging C1. In the hold phase, Q1 is deactivated, leaving Q1 Id (< 100 pA) and Q2 Igss (< 100 pA) as the only discharge paths. Q2 serves a buffering function, supplying feedback to the LM101 and providing output current from its source.

The circuit employs JFETs (Junction Field Effect Transistors) Q1 and Q2 to effectively manage the charging and discharging of the sample and hold capacitor, C1. The operation of Q1 during the sample phase is crucial, as it allows for rapid charging of C1 by offering a low on-resistance path, known as rds(on). This ensures that the capacitor reaches the desired voltage level quickly and efficiently.

Once the sample phase is complete, Q1 is turned off, effectively isolating C1 and preventing any significant discharge except through minimal leakage currents associated with Q1 and Q2. The leakage currents, Id for Q1 and Igss for Q2, are both kept below 100 picoamperes, ensuring that the charge stored in C1 remains stable during the hold phase. This feature is essential for applications requiring precision in sampled signals, as it minimizes voltage drift over time.

Q2's role as a buffer is also significant. It not only provides feedback to the operational amplifier LM101 but also delivers the output current necessary for downstream circuitry. This buffering action helps to maintain signal integrity and ensures that the output remains stable, regardless of variations in the load conditions. The configuration of Q2 enhances the overall performance of the sample and hold circuit, allowing it to operate effectively within a variety of electronic systems.

In summary, the combination of Q1 and Q2 in this configuration allows for efficient sample and hold operations, maintaining high fidelity in signal processing applications while managing leakage currents effectively.The JFETs, Ql and Q2, provide complete buffering to Cl, the sample and hold capacitor. During sample, Ql is turned on and provides a path, rds(on), for charging Cl. During hold, Ql is turned off, thus leaving Ql Id (< 100 pA) and Q2 Igss (< 100 pA) as the only discharge paths Q2 serves a buffering function so feedback to the LM101 and output current are supplied from its source.