Odd-number-counter-divider

Description: This circuit, illustrated symmetrically, divides an input by virtually any odd number. The circuit counts n + 1/2 clocks twice to achieve the desired divisor. By selecting the appropriate n, which is the decoded output of the LS161 counter, divisors ranging from 3 to 31 can be obtained. The circuit, as depicted, divides by 25; higher divisors can be achieved by cascading additional LS161 counters. The counter and IC5A form the n + 1/2 counter. Once the counter reaches the decoded count, n, IC5A ticks off an additional 1/2 clock, which clears the counter and puts it in hold. Additionally, IC5A clocks IC5B, which alters the clock phasing through the XOR gate, IC1. The next edge of the input clocks IC5A, which re-enables the counter to start counting for an additional n + 1/2 cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis indicates that the maximum input frequency is between 7 and 8 MHz.

This circuit utilizes a combination of LS161 binary counters to achieve division of an input signal by odd numbers in a flexible manner. The primary function revolves around the counting mechanism, which is designed to count n + 1/2 clock cycles. The LS161 is a synchronous 4-bit binary counter that allows for the selection of specific counts through its decoded outputs, enabling the selection of divisors ranging from 3 to 31.

In this configuration, the circuit is set to divide by 25. To achieve this, the counter is configured to count up to a predetermined value, n, which is derived from the configuration of the LS161 outputs. Once the counter reaches this value, IC5A generates an additional 1/2 clock pulse, effectively resetting the counter and placing it in a hold state, ensuring that the output remains stable until the next counting cycle begins.

The operation of the circuit is further enhanced by the inclusion of IC5B, which receives a clock signal from IC5A. This component is responsible for altering the phase of the clock signal through an XOR gate, specifically IC1. The clock phasing adjustment allows for precise timing control, which is critical in high-frequency applications.

The design has been validated for operation at frequencies up to 16 MHz; however, practical considerations limit the maximum input frequency to between 7 and 8 MHz, as indicated by a worst-case timing analysis. This analysis accounts for potential delays and signal integrity issues that may arise at higher frequencies, ensuring reliable operation within the specified limits.

Overall, this circuit provides a robust solution for frequency division, allowing for versatile applications in digital electronics where odd-numbered division is required. The cascading capability of the LS161 counters further extends the range of possible divisors, making this circuit adaptable for various operational needs.This circuit, shown symmetrically, divides an input by virtually any odd number. The circuit counts n + 1/2 clocks twice to achieve the desired divisor. By selecting the proper n, which is tbe decoded output of the LS161 counter, you can obtain divisors from 3 to 31. The circuit, as shown, divides by 25; you can obtain higher divisors by cascading additional LS161 counters.

The counter and IC5A form the n + 1 /z counter. Once the counter reaches the decoded count, n, IC5A ticks off an additional 1/z clock, which clears the counter and puts it in hold. Additionally, IC5A clocks IC5B, which changes the clock phasing through the XOR gate, IC1. The next edge of the input clocks IC5A, which reenables the counter to start counting for an additional n + "lz cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis reveals that tbe maximum input frequency is between 7 and 8 MHz.