2115

Technical Summary: ADSP-2115 Digital Signal Processor

Overview

The ADSP-2115 is a member of the ADSP-2100 Family of single-chip microcomputers, specifically optimized for high-performance digital signal processing (DSP) and numeric-intensive applications. Built upon a common DSP core architecture, the ADSP-2115 integrates computation units, data address generators, and a program sequencer with enhanced on-chip memory and peripheral features. This processor is designed to deliver high-speed processing with low power consumption, making it ideal for real-time DSP applications in telecommunications, audio processing, and industrial control systems.

The ADSP-2115 distinguishes itself with a 25 MIPS performance capability and a 40 ns maximum instruction cycle time. Its Harvard architecture, featuring separate program and data memory buses, enables simultaneous access to instructions and data for maximum throughput. The processor also includes specialized DSP features such as hardware-supported circular buffering and bit-reverse addressing, which are essential for efficient FFT and digital filter implementations.

Key Features

• High Performance Processing: 25 MIPS sustained performance with 40 ns instruction cycle time
• Advanced Architecture: Harvard architecture with three-bus structure (program memory, data memory, and I/O buses)
• On-Chip Memory: Integrated program and data RAM with automatic booting capability from external byte-wide memory
• Efficient Addressing: Dual data address generators supporting modulo (circular) and bit-reverse addressing modes
• Zero-Overhead Looping: Hardware support for single-cycle loop setup and execution
• Serial Communication: Double-buffered serial ports with hardware companding (μ-law/A-law), automatic data buffering, and multichannel operation
• Host Interface: ADSP-2111-compatible host interface port for easy connection to host processors
• Programmable Timer: On-chip timer for precise event timing and control

Applications

The ADSP-2115 is particularly suited for applications requiring real-time digital signal processing with moderate to high computational demands:

• Telecommunications systems (modems, digital subscriber line equipment)
• Audio signal processing (effects processors, digital mixers)
• Speech recognition and synthesis systems
• Industrial control and instrumentation
• Medical signal processing (ultrasound, ECG analysis)
• Radar and sonar signal processing
• Image processing systems

Electrical Characteristics

Absolute Maximum Ratings

• Supply Voltage (VDD): -0.3V to +7.0V
• Input Voltage: -0.5V to VDD + 0.5V
• Operating Temperature Range: -40°C to +85°C
• Storage Temperature Range: -65°C to +150°C

Recommended Operating Conditions

• Supply Voltage: 4.75V to 5.25V
• Operating Temperature: Commercial (0°C to +70°C) or Industrial (-40°C to +85°C)
• Clock Frequency: Up to 25 MHz

Power Consumption

• Active Mode: 500 mW typical at 25 MHz
• Idle Mode: 200 mW typical
• Power-Down Mode: 50 μW typical

Timing Characteristics

• Instruction Cycle Time: 40 ns (25 MHz operation)
• Serial Port Clock Rate: Up to 12.5 MHz
• Host Interface Access Time: 50 ns maximum

Package Information

The ADSP-2115 is available in several package options to accommodate different application requirements:

Plastic Leaded Chip Carrier (PLCC)

• 68-lead package
• JEDEC Standard 68-pin PLCC footprint
• Body Size: 24.23 mm × 24.23 mm
• Lead Pitch: 1.27 mm
• Operating Temperature: Commercial and Industrial grades available

Ceramic Pin Grid Array (PGA)

• 68-pin ceramic package
• High-reliability option for military and aerospace applications
• Body Size: 27.94 mm × 27.94 mm
• Pin Pitch: 2.54 mm
• Extended temperature range: -55°C to +125°C

Surface Mount Options

• Thin Quad Flat Pack (TQFP) available for space-constrained applications
• 68-lead package with 0.8 mm lead pitch
• Body Size: 14 mm × 14 mm

Architectural Details

The ADSP-2115's architecture is optimized for DSP algorithms through several key features:

Computational Units

• ALU with 16-bit/32-bit operation
• Multiplier/Accumulator (MAC) with 16-bit × 16-bit multiply and 40-bit accumulation
• Barrel shifter for efficient scaling operations
• Dual data address generators allowing simultaneous operand fetches

Memory Organization

• 1K × 24-bit on-chip program RAM
• 1K × 16-bit on-chip data RAM
• 16-bit external memory interface
• Program memory can store both instructions and data coefficients

Program Control

• Two-level interrupt nesting
• Single-cycle context switch
• Zero-overhead looping hardware
• Flexible conditional execution

Development Support

The ADSP-2115 is supported by comprehensive development tools:

• Cross-compilers and assemblers for C and assembly programming
• Cycle-accurate simulators
• Emulation pods for hardware debugging
• Evaluation boards with full-featured I/O capabilities
• DSP libraries with optimized functions for common algorithms

Conclusion

The ADSP-2115 represents a balanced combination of performance, integration, and power efficiency in the ADSP-2100 family. Its architectural features specifically target digital signal processing applications while maintaining flexibility for general-purpose numeric processing. With its integrated memory, efficient I/O capabilities, and robust development support ecosystem, the ADSP-2115 continues to be a preferred choice for engineers designing demanding DSP applications across multiple industries.