8 Channel PWM with AT90S1200

Description: The assembly code given here was written to see what it would take to make an AT90S1200 generate 8 channels of proper PWM. In this case, by proper, I mean with the maximum high frequency content consistent with the needed duty cycle and give clock. Take a look at the scope shots below and notice that when the data value is =$02, there pulse frequency is twice that which occurs when the data value is =$01. The significance of this is that the percent of ripple voltage out of the low pass filter stays much more constant as the data values change than they would with a conventional PWM that merely varies the width of a single pulse (see the auto zero code for the RF Field Strength Probe for an example of code that does this). Take a look at the pictures below to see the effect. When running with a 4 MHz clock, this code provides 8 channels of 8 bit resolution with a 60 Hz minimum frequency (which occur at data values of $01 and $FF. By adjusting the interrupt timer reload value, the minimum frequency can be taken to 100 Hz, but at the cost of time available for other tasks. Of course, changing the clock oscillator frequency is another way to increase the minimum frequency. The code was originally written for and tested on an AT90S1200A, I also merged it with a monitor program and tested it on an AT90S2313. Thus, it can be adapted to a variety of AVR chips, including those with really limited resources such as the ATTiny12 easily. The code Here is the assembly code for the PWM routine. This code is an example program with the routines necessary to make the PWM machine work, but it only drives values that are preprogrammed in as constants at assembly time. Adding an interface so the PWM values can be adjusted in real time is left as an exercize for the student. Performance Step size is very good. The largest one I found was about 1/2 lsb (See the table near bottom of this page). I measured this with a single pole RC filter and a 3-1/2 digit DVM, so I suspect that the apparent 1/2 lsb step error is actually much smaller and the error is really the result of the resolution of the measurement. PWM dacs can be very, very linear. What was surprising was to find some cross talk from another channel. All these signals were measured in PORTB bit 4, and while changing the values of bits 0,1,2,3,5,and 6 had not apparent affect on bit 4's voltage, changing bit 7 from $00 to $FF caused about a 1.5 lsb error in bit 4's voltage. Maybe this is a case for buffering PWM outputs in critical situations (then again it was critical, maybe a real DAC would be better).

The assembly code for the AT90S1200 is designed to generate an 8-channel Pulse Width Modulation (PWM) output, allowing for high-frequency control of the duty cycle across multiple channels. By utilizing an AVR microcontroller with an operating frequency of 4 MHz, the system achieves an 8-bit resolution for each channel, with a minimum output frequency of 60 Hz, which can be increased to 100 Hz by adjusting the interrupt timer reload value. This flexibility in frequency adjustment is crucial for applications requiring precise control over signal timing while maintaining the ability to perform other tasks.

The PWM generation technique employed here is noteworthy for its ability to maintain a constant ripple voltage at the output of a low-pass filter, even as the duty cycle values change. This is in stark contrast to conventional PWM methods that typically vary pulse width, resulting in greater fluctuations in output voltage. The performance of the PWM output has been characterized by a step size of approximately 1/2 least significant bit (LSB), indicating a high degree of linearity in the output response, which is essential for applications requiring fine control.

Additionally, the code's implementation on both the AT90S1200A and AT90S2313 demonstrates its adaptability across various AVR microcontrollers, including those with limited resources such as the ATTiny12. This versatility ensures that the PWM routine can be integrated into a wide range of projects, from simple applications to more complex systems.

It is important to note that some cross-talk was observed during testing, particularly affecting PORTB bit 4 when bit 7 was toggled. This suggests that in applications where precision is critical, buffering the PWM outputs may be necessary to mitigate interference between channels. The assembly code serves as a foundational example, with the potential for further enhancements, such as real-time adjustment interfaces for PWM values, which could significantly increase the functionality and usability of the PWM system in practical applications.The assembly code given here was written to see what it would take to make an AT90S1200 generate 8 channels of proper PWM. In this case, by proper, I mean with the maximum high frequency content consistent with the needed duty cycle and give clock.

Take a look at the scope shots below and notice that when the data value is =$02, there pulse frequency is twice that which occurs when the data value is =$01. The significance of this is that the percent of ripple voltage out of the low pass filter stays much more constant as the data values change than they would with a conventional PWM that merely varies the width of a single pulse (see the auto zero code for the RF Field Strength Probe for an example of code that does this).

Take a look at the pictures below to see the effect. When running with a 4 MHz clock, this code provides 8 channels of 8 bit resolution with a 60 Hz minimum frequency (which occur at data values of $01 and $FF. By adjusting the interrupt timer reload value, the minimum frequency can be taken to 100 Hz, but at the cost of time available for other tasks.

Of course, changing the clock oscillator frequency is another way to increase the minimum frequency. The code was originally written for and tested on an AT90S1200A, I also merged it with a monitor program and tested it on an AT90S2313. Thus, it can be adapted to a variety of AVR chips, including those with really limited resources such as the ATTiny12 easily.

The code Here is the assembly code for the PWM routine. This code is an example program with the routines necessary to make the PWM machine work, but it only drives values that are preprogrammed in as constants at assembly time. Adding an interface so the PWM values can be adjusted in real time is left as an exercize for the student.

Performance Step size is very good. The largest one I found was about 1/2 lsb (See the table near bottom of this page). I measured this with a single pole RC filter and a 3-1/2 digit DVM, so I suspect that the apparent 1/2 lsb step error is actually much smaller and the error is really the result of the resolution of the measurement. PWM dacs can be very, very linear. What was surprising was to find some cross talk from another channel. All these signals were measured in PORTB bit 4, and while changing the values of bits 0,1,2,3,5,and 6 had not apparent affect on bit 4's voltage, changing bit 7 from $00 to $FF caused about a 1.5 lsb error in bit 4's voltage.

Maybe this is a case for buffering PWM outputs in critical situations (then again it was critical, maybe a real DAC would be better).