Dual-Slope Integrating ADC

Description: A column-parallel analog-to-digital converter (ADC) has been developed for integration with CMOS active pixel sensors (APS). The design objectives focused on simplicity, compactness, moderate speed (greater than 10 kHz), current input, and acceptable accuracy (6 bits). The ADC is intended to produce a rough digital output from pixels that primarily serve other functions such as image quality sensing and stereo vision. The design employs a current input, which significantly reduces the area required for implementation compared to a dual-slope ADC with a voltage input from a high impedance source, which necessitates a transconductance amplifier for voltage integration over time.

The ADC operates in three steps. In the first step, switch S1 is activated to reset the capacitor to a known, fixed voltage, after which S1 is turned off. In the second step, switch S2 is engaged for a predetermined time period, during which the voltage change across the capacitor is directly proportional to the input current, assumed to remain constant during the integration period. In the third step, the capacitor is discharged using a known reference current (I2), and the time taken for the capacitor to return to the original reference voltage (V1) is directly proportional to the input current. This timing is independent of the capacitor's value (C1), disregarding non-idealities in the current sources. The cycle then repeats.

The voltage on the capacitor is compared against the reference voltage using a latched comparator, which is clocked 64 times (representing 6 bits) during the discharge cycle. The number of clock cycles required to achieve a high output from the comparator indicates the ADC's output value. The design includes only a comparator, a capacitor (implemented as a PFET capacitor), two current mirrors, and several switches. The architecture allows multiple ADCs to share a single counter, a bias circuit for the comparator's current source, and a bias circuit for the discharge circuit, resulting in a compact ADC cell size of 228 x 99 µm². When arranged, N ADCs occupy an area of 228 x (N x 99) µm². The reference current is generated by a cascode mirror controlled by a b-multiplier reference. The input current is mirrored using cascode mirrors, enabling operation with sources having lower output impedances than would be feasible with direct integration.

The control circuitry accommodates two inputs: a clock (T=48 ns) and a reset signal, which must be held high for at least one clock period during power-up. After the initial reset, the control circuitry generates the necessary non-overlapping clock signals. The core of the control circuit is a 6-bit counter that counts upwards from 0 to 63, resetting to 0 after reaching the maximum count, for three complete cycles (reset, charge, and discharge) for each conversion. The control circuit schematic and layout are included in the appendix. A single counter bit-slice schematic and layout are also provided. Additional clocks for the main clock, charge clock, and reset clock are generated using a non-overlapping clock generation circuit, detailed in the appendix. Currently, the chip does not retain the converted values produced by the ADC; the output reflects the counter's value when the comparator first outputs a high pulse. Future enhancements may include a 6-bit latch for each ADC to enable storage of the digital output. An output multiplexer could facilitate the integration of hundreds of ADCs on a single 2.25 mm² MOSIS TinyChip. The ADC was designed for fabrication using the AMI C5N 0.5 µm process (l=0.6 µm).A column-parallel analog-to-digital converter was designed for use with CMOS active pixel sensors (APS). The design goals included simplicity, small size, moderate speed (>10kHz), current input, and reasonable accuracy (6-bits).

The ADC was designed to get a rough digital output from pixels that serve some other primary function (image quality sen sing, stereo vision, etc. ). The ADC was designed with a current input. This greatly decreases the area necessary to implement the ADC; a dual-slope ADC with a voltage input (from a high impedance source) requires a transconductance amplifier in order to integrate the voltage over time. The ADC works in three steps. During the first step switch S1 is turned on, resetting the capacitor to a known, fixed voltage. Switch S1 is then turned off. During the second step switch S2 is turned on for a fixed time period. The change in voltage on the capacitor is then directly proportional to the input current (which is assumed to be constant over the integration time).

During the third step the capacitor is discharged with a known reference current I2. The time taken for the capacitor to reach the original reference voltage V1 is then directly proportional to the input current. This time is independent of the value of capacitor C1 (ignoring non-idealialities is the current sources).

The cycle then repeats again. A more detailed schematic and layout can be seen in the appendix. The voltage on the capacitor is compared against the reference voltage using a latched comparator (the layout and schematic are shown in the appendix) [ [1] ]. The comparator is clocked 64 times (representing 6 bits) during the discharge cycle. The number of latches needed before a high output is reached represents the output value of the ADC. The design required only a comparator, a capacitor (implemented as a PFET capacitor), two current mirrors, and several switches.

As much of the necessary circuitry was separated from the single ADC as possible, such that N ADCs may share one counter, a bias circuit for the comparator`s current source, and a bias circuit for the discharge circuit. This enabled the single ADC cell to be only 228 x 99l2. The ADCs were designed to abut such that N ADCs take 228 x (N x 99)l2 of area. The reference current is produced by a cascode mirror, whose current is controlled by a b-multiplier reference (see schematic and layout appendix) [ [2] ].

The input current was mirrored using cascode mirrors, allowing the circuit to operate on sources with lower output impedance than would be possible if the input current were directly integrated. The control circuitry was designed to accept two inputs: a clock (T=48ns) and a reset signal. The reset signal must be held high for at least one clock period at power up. After the initial reset the control circuitry generates all of the necessary non-overlapping clocks. The central component of the control circuit is the 6 bit counter; this counter counts upwards (incrementing from 0 to 63, with the next increment going to 0) for three full cycles (reset, charge, and discharge) for each conversion.

The control circuit schematic and layout are shown in appendix. A single counter bit-slice (schematic and layout) can also be seen in the appendix. Compliments were required for the main clock, the charge clock, and the reset clock. These were generated using a non-overlapping clock generation circuit, shown in appendix. Currently the chip does not store the converted values produced by the ADC. The output value is the value of the counter when the comparator first outputs a high pulse. Future improvements could include a 6-bit latch for each ADC to allow for storage of the digital output. An output multiplexer could allow hundreds of ADCs to fit on a single 2. 25mm2 MOSIS TinyChip . The ADC was designed for fabrication on the AMI C5N 0. 5mm process (l=0. 6mm). The area used by 8 ADC cells and the control