LC compliant boost converter circuit diagram

Description: The main ΣΔ loop operates in steady state and is fully controlled by summing comparator Q2. This comparator amplifies the ripples of the sensed inductor current and output voltage with gains KI and KV, respectively, to generate an internal variable s. This variable s is regulated to zero by the feedback control action of Q2, similar to conventional sliding-mode control. In steady state, auxiliary switch MPP3 remains open, and the bypass ΣΔ block containing comparator Q1 is inactive. The main loop ensures wide LC filter compliance and low output voltage ripple, adhering to the principles of sliding-mode ΣΔ control. However, the transient response is slow, as it is designed to meet the worst-case LC specifications. This slow response is compensated for by the fast bypass ΣΔ loop, which operates only during transient events. The bypass ΣΔ loop is controlled by comparator Q1, which senses and regulates the output voltage through the duty-cycle of switch MPP3. When the output voltage drops below a predefined window limit set by Q1, the bypass loop regulates the output voltage (VS) to VREF, regardless of the inductor current, thereby increasing the average inductor current since its dIL/dt is predominantly unidirectional. This results in the inductor current exceeding its minimum average value ILMIN (the inductor current IL equals ILMIN during steady-state conditions) and only decreases when the output voltage returns to the specified window limits, at which point MPP3 is disabled. Comparator Q2 regulates the sensed inductor current to its reference value, which is the DC value of the sensed current. This current loop operates independently and is self-sustaining, maintaining a regulated and constant inductor current. A higher-than-minimum inductor current results in increased power losses and a higher output voltage ripple, necessitating a reduction of the inductor current to ILMIN.

The described circuit employs a ΣΔ modulation technique for controlling the output voltage and inductor current in a power supply application. The main ΣΔ loop, managed by comparator Q2, effectively stabilizes the system by generating an internal variable s that is maintained at zero through feedback control. This feedback mechanism is crucial for ensuring that the output voltage remains stable under varying load conditions.

In steady state, the auxiliary switch MPP3 is kept open, preventing unnecessary switching losses and allowing the main loop to operate efficiently. The integration of the bypass ΣΔ loop, activated during transient events, enhances the system's response time by quickly adjusting the output voltage. Comparator Q1 plays a vital role in this process, detecting when the output voltage falls below a set threshold and adjusting the duty cycle of MPP3 to restore the voltage to the reference level VREF.

The operation of the bypass loop is particularly significant during load transients, where rapid changes in output voltage can occur. By forcing an increase in the average inductor current, the bypass mechanism compensates for these transients, ensuring that the output voltage remains within acceptable limits. The regulation of the inductor current by comparator Q2 ensures that the current remains at a constant value, preventing excessive power losses and output voltage ripple.

The overall design of this circuit exemplifies an effective approach to power management, balancing the need for fast transient response with the stability and efficiency of the main operating conditions. The careful regulation of inductor current and output voltage through the use of ΣΔ control techniques demonstrates a sophisticated understanding of power electronics principles.The main ΣΔloop, which again operates in steady state, is fully controlled by summing comparator Q2, which amplifies the ripples of the sensed inductor current and output voltage by gains KI and KV, respectively, to generate an internal variable s. This variable s , is regulated to zero by the feedback control action of Q2, as in conventional sliding-mode control.

In steady state, auxiliary switch MPP3 is always open and the bypass ΣΔ block containing comparator Q1 is inactive. The main loop gives wide LC filter compliance and low output voltage ripple since it adheres to the teachings of sliding-mode ΣΔ control. However, the transient response is slow because it is defined to meet the requirements of the worst-case LC specifications.

This slow response is corrected using the fast bypass ΣΔ loop during transient events. The bypass ΣΔ loop, operating during transient events only, is controlled by comparator Q1, which senses and controls the output voltage through the duty-cycle of switch MPP3. During bypass conditions, when the output voltage drops below the predefined window limit set by Q1, the bypass loop regulates the output voltage (VS) to VREF, irrespective of the inductor current, forcing the average inductor current to increase, since its dIL/dt is now mostly unidirectional.

This current consequently increases beyond its minimum average value ILMIN (inductor current IL equals ILMIN during steady-state conditions) and only drops back down when the output voltage again reaches its prescribed window limits, at which point MPP3 is disabled. Comparator Q2 only regulates the sensed inductor current to its reference value, which is the DC value of the sensed current.

This current loop is therefore independent and self-sustaining and the inductor current, as it is, is regulated and constant. A higher-than-minimum inductor current leads to increased power losses and a higher output voltage ripple, which is why the inductor current must be ultimately reduced to ILMIN.