16 Step Sequencer Quantized Vari-Clock Module

Description: A mechanism allows a standard potentiometer to function as a digitized potentiometer, converting each setting into a number between 0 and 15. This information is utilized to determine the duration for each step. An analog-to-digital converter (ADC) is designed to quickly convert the potentiometer's position into a number within this range, achieving this within approximately 300 microseconds. The ADC employs a digital-to-analog converter (DAC) to generate a stepped ramp voltage for comparison with the input signal. When the stepped voltage from the DAC exceeds the input level by a few millivolts, the current count from the DAC is latched, yielding the digital code for the ADC. The circuitry is detailed below, featuring components U1, U2, U3, and U4. U2 is a CD40193 binary counter, with its outputs connected to a classic R/2R network (comprised of resistors R6, R7, R12, R16, R15, R18, R19, R20, and R22) that translates the binary output into a voltage level linearly correlated with the binary count (this is referred to as the DAC portion of the ADC). Resistor R23 (470K to +12V) provides a positive bias to the output of the R/2R ladder, facilitating zero-volt sensing by the ADC. The counter is clocked by U1-A, C17, and R26, configured as a simple phase shift oscillator. The CD40193 counts upward, resulting in a positive-going stepped ramp wave from the R/2R ladder, with voltage levels corresponding to the binary output of the counter. U3-A buffers the R/2R network output and feeds it to the non-inverting input of U3-B via a 10K resistor (R17). The inverting input of U3-B is connected to the level-shifted input voltage (Point DV), which links to the common I/O of U8, a CD4067 16-channel analog switch. The switch connects the wipers of the potentiometers used for setting step durations. These pots function as variable voltage dividers, providing between 0V and 12V to the wiper as the pot is rotated from counter-clockwise to clockwise. The CD4067 connects one pot wiper at a time to its common I/O (pin 1) based on the binary code applied to its A through D channel selection inputs. For instance, a code of 0000 connects pin 9 to the common I/O point (pin 1). As the CD4067 connects a pot wiper to the common I/O point, the voltage on the wiper is applied to circuit point DV (duration voltage). This voltage is slightly attenuated by U3-C and resistors R8 and R9, configured as an inverting attenuator (with a gain of -0.56). Trimmer R5 is utilized to adjust the voltage, ensuring the full rotation of the potentiometer smoothly transitions through the 16 settings. U3-D re-inverts and buffers the voltage, ensuring its output aligns with the voltage at point DV. To fully utilize the rotation of the duration pots for setting the digital code, trimmer R5 requires adjustment. Calibration of the span trim is straightforward: with the sequencer in step mode, select any position and turn the corresponding duration pot fully up. Adjust R5 until all binary indicator LEDs (LED1 to LED4) illuminate. Subsequently, adjust the pot until the least significant bit LED (LED1) turns off, then fine-tune R5 so that LED1 just turns on, and continue adjusting slightly further until all LEDs are solidly lit with the pot fully clockwise. During operation, it is essential to adjust the duration settings to ensure the binary count indicator LEDs remain consistently illuminated, confirming that the settings are at optimal points rather than at intermediary positions. With practice, this adjustment becomes intuitive. The output of U3-D is fed into the inverting input of U3-B, which operates as a comparator. During typical operation, the output from U3-A is compared against the voltage present at U3-D's output.

The described circuit effectively integrates analog and digital components to create a responsive and precise control mechanism for step durations based on potentiometer settings. The use of a binary counter and R/2R ladder network allows for accurate voltage representation of digital values, while the CD4067 switch facilitates seamless selection of different potentiometer outputs. The careful calibration of the trimmer resistors ensures that the system operates within the desired parameters, providing reliable performance across the full range of potentiometer adjustments. The design emphasizes the importance of maintaining signal integrity through buffering and appropriate voltage scaling, which contributes to the overall functionality and efficiency of the mechanism.A mechanism by which a normal pot could be used as a digitized pot since I need each pot`s setting to be converted to a number between 0 and 15. I use that information to determine the duration for each step. I accomplished this by designing an analog to digital convertor that could take a pot`s position and convert it to a number between 0 and 15 relatively quickly (within 300 microseconds or so).

The A to D convertor is the type that uses a D to A convertor to create a stepped ramp voltage to which the input is compared. When the stepped voltage output of the D to A convertor is a few millivolts above the current input level the current count from the D to A convertor is clocked into a latch.

The latched output is the D (digital code) in this A to D convertor. The circuitry is described below. The A to D convertor is realized by U1, U2, U3 and U4. U2 is a CD40193 binary counter whose outputs are connected to the classic R/2R network (made up of R6, R7, R12, R16, R15, R18, R19, R20 and R22) which converts the binary output to a voltage level which is linearly related to the binary count (I refer to this as the D to A element of the A to D convertor). R23 (470K to +12V) causes the output of the R/2R ladder to be positively biased a bit. This is to allow sensing of zero volts by the A to D convertor. The counter is clocked by U1-A, C17 and R26 which are wired as a simple phase shift oscillator. The CD40193 is wired to count upward and thus the output of the R/2R ladder (D to A) is a positive going stepped ramp wave whose voltage levels correspond with the binary output of the counter.

U3-A buffers the R/2R network output and applies it to the non-inverting input of U3-B via 10K resistor R17. U3-B`s inverting input is connected to the level shifted input voltage (Point DV). Point DV connects to the common I/O point on U8 CD4067 16 channel analog switch. The inputs to the CD4067 are the wipers of the pots used to set the step durations. The pots are wired as variable voltage dividers delivering between 0V and 12V to the wiper as the pot is advanced from CCW to CW.

The CD4067 connects one of the pot wipers at a time to it`s common I/O (pin 1) depending on the binary code applied to it`s A thru D channel selection inputs. For example code 0000 connects pin 9 to the common I/O point pin 1. As the CD4067 connects one of the pot wipers to the common I/O point the voltage on the wiper is applied to circuit point DV (duration voltage).

The voltage is attenuated slightly by U3-C and resistors R8 and R9 wired as an inverting attenuator (gain of -. 56). Trimmer R5 is used to trim the voltage to allow the full rotation of the pot to take the duration smoothly through the 16 settings.

U3-D re-inverts and buffers the voltage so that it`s output corresponds with the sense of the voltage applied to point DV. In order to utilize the full rotation of the duration pots for setting the digital code you need to adjust trimmer R5.

Calibrating the span trim is easy. With the sequencer in step mode, step to any position. Turn that position`s duration pot all the way up. Adjust R5 until all of the binary indicator LEDs (LED1 thru LED4) are lit. Now adjust the pot until the 1`s place LED (LED1) goes out then adjust R5 so that the 1`s place LED (LED1) just comes on and then turn it a wee bit further so that all the LEDs are solidly lit when the pot is adjusted fully clockwise. During use you will want to adjust the duration settings so that the binary count indicator LEDs are solidly on.

You want to make sure you are at the sweet spots of the pot`s adjustment and not at a quasi-in-between setting. With use of the feature this becomes second nature. U3-D`s output is applied to the inverting input of U3-B which is wired as a comparator. During normal operation the output of U3-A is compared to the voltage present at U3-D`s out