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Description: The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin, the CLKOUT is delayed by a 1.3 mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly, for every rising edge on the DLYCTRL pin, the CLKOUT is advanced by a 1.3 mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any other clock in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Additionally, it provides the capability to program a fixed delay by supplying the proper number of edges on the DLYCTRL pin while strapping the LEADLAG pin to DC high or low. Further possible applications include aligning the rising edge of the output clock signal to the input clock rising edge, avoiding PLL instability in applications that require very long PLL feedback lines, isolating jitter and digital switching noise, and limiting jitter in systems with good parts per million (ppm) frequency stability. The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The pre-divider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLKOUTB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to 240 MHz. The selection of pins MULT[0:1] and P[1:2] determines the multiplication values of 1, 2, 4, or 8. The CDCF5801 offers several power-down/high-impedance modes, selectable by pins P0, STOPB, and PWRDN. Another unique capability of the CDCF5801 is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDs, LVPECL, or HSTL/SSTL signaling. The CDCF5801 is characterized for operation over free-air temperatures of -40°C to 85°C.

The CDCF5801 is a versatile clock management device designed for applications requiring precise clock signal manipulation. It features advanced clock multiplication and division capabilities, allowing it to generate output frequencies that are critical in high-speed digital systems. The device's phase aligner function is particularly noteworthy, enabling fine-tuning of clock signals with a resolution of 1.3 mUI, which is essential for maintaining signal integrity in high-performance applications.

The architecture of the CDCF5801 includes multiple input and output configurations, with two main outputs, CLKOUT and CLKOUTB, capable of being configured for single-ended or differential signaling. This flexibility allows the device to interface with various signaling standards, including LVDs, LVPECL, and HSTL/SSTL, making it suitable for a wide range of digital communication applications.

The pre-divider and post-divider functionalities provide further customization of output frequencies, allowing designers to select from a range of multiplication and division ratios. This adaptability is crucial for meeting the specific frequency requirements of different systems while ensuring minimal jitter transfer from input to output.

Power management features, including selectable power-down and high-impedance modes, enhance the device's usability in power-sensitive applications. The ability to adjust the common-mode range of the REFCLK input by varying the VDDREF voltage increases the overall robustness of the device in various operating environments.

Overall, the CDCF5801 is designed to deliver high performance, low jitter, and flexible clock management solutions for advanced electronic systems, ensuring reliable operation across a wide temperature range and diverse applications.The CDCF5801 provides Clock multiplication from a reference Clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1. 3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1. 3-mUI step size as long as the LEADLAG input detects a low signal at the time o f the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1. 3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the Clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low.

Further possible applications are: Aligning the rising edge of the output Clock signal to the input Clock rising edge Avoiding PLL instability in applications that require very long PLL feedback lines Isolation of jitter and digital switching noise Limitation of jitter in systems with good ppm frequency stability The CDCF5801 provides Clock multiplication and division from a reference Clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with Clock input references (REFCLK) ranging from 12.

5 MHz to 240 MHz. The selection of pins MULT[0:1] and P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801 offers several power-down/ high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801 is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin.

The Clock signal outputs CLKOUT and CLKOUTB CAN be used independently to generate single-ended Clock signals. The CLKOUT/CLKOUTB outputs CAN also be combined to generate a differential output signal suitable for LVDs LVPECL, or HSTL/SSTL signaling.

The CDCF5801 is characterized for operation over free-air temperatures of -40C to 85C.