Full bridge class d amp using 555 timer

Description: This document presents an improvised circuit model designed to eliminate unwanted DC offset voltage from the output, which affects previously discussed circuits. All prior circuits were intended as low-power Class D amplifier sources suitable for driving headphones through a coupling capacitor, thus ignoring DC offset due to the capacitor's presence. The schematic provided is a reference design that includes a DC offset adjustment potentiometer and a high-power FET driver from MICREL, which has been substituted with a power FET to simplify amplification and reduce costs. This design eliminates the need for an expensive FET driver with a level shifter, as the PWM source requires the same rail supply as the output FET. Although MICREL's MIC4451 features a built-in cross-conduction minimizer, an additional option is offered to include a CD4030 exclusive OR gate for enhanced safety. This gate also serves as a phase splitter, necessary for the two power switches configured in a full-bridge topology. It is assumed that the builder of this circuit possesses knowledge of concepts such as ringing, RFI, and EMI; therefore, adequate power supply bypass capacitors and short copper trace lengths must be utilized. Constructing a Class D amplifier from scratch presents numerous challenges and requires a degree of courage, but it may appeal to adventurous hobbyists seeking alternatives to linear designs. The schematic necessitates minor adjustments on the 555 timer side due to the supply voltage being set at 12 volts. In addition to the offset adjustment potentiometer (50% adjust pot via R3), careful attention must be paid to pin 5, the inverting input of the internal comparator, which is connected to a voltage divider that also requires adjustment. Tuning the R1 potentiometer will aid in achieving the desired configuration. The sawtooth voltage variations from pin 6 do not conform to the required 2/3 VCC of the timer; instead, they are set to be less than 2/3 VCC to minimize distortion. For optimal performance, substituting an op-amp for the 2N3904 transistor is recommended. An LTspice simulation is provided for experimentation. Either R2 or C2 can be modified for dead time adjustment to achieve the lowest possible distortion without cross-conduction. The RC delay network and its ORed diode resistor combination from the output can be omitted if desired, using it solely as a phase splitter. A correction has been made in the schematic: THRS and TRIG must be connected to the center of the potentiometer rather than to D1 and R3.

The circuit design focuses on addressing the issue of DC offset in a Class D amplifier configuration, which is particularly critical in audio applications where fidelity is paramount. The use of a coupling capacitor is a standard method to block DC components while allowing AC signals to pass. The integration of a DC offset adjustment potentiometer allows for fine-tuning of the output, accommodating various load conditions and ensuring that the output remains within acceptable voltage levels.

The choice of a high-power FET driver from MICREL, despite being substituted with a simpler power FET, exemplifies a practical approach to circuit design. This substitution not only reduces costs but also simplifies the design process, making it more accessible for hobbyists and engineers alike. The design leverages the characteristics of PWM signals, which are essential for efficient power amplification in Class D amplifiers. The inclusion of a CD4030 exclusive OR gate enhances the safety of the circuit by providing a mechanism to prevent cross-conduction, which can lead to inefficiencies and potential damage to the components.

Furthermore, the careful consideration of component placement and trace lengths is vital in minimizing electromagnetic interference (EMI) and radio frequency interference (RFI). This is especially important in audio applications, where noise can significantly degrade performance. The recommendation for short copper traces and adequate bypass capacitors emphasizes the importance of good layout practices in high-frequency circuits.

The adjustments to the 555 timer, particularly concerning the sawtooth waveform generation, underscore the need for precision in timing circuits. The recommendation to replace the 2N3904 with an op-amp for improved performance highlights an understanding of operational amplifier advantages, such as higher gain and lower distortion characteristics. The use of LTspice for simulation purposes allows builders to experiment with different configurations and component values, fostering a deeper understanding of the circuit's behavior before physical implementation.

Overall, this circuit design presents an innovative approach to building a Class D amplifier, addressing common challenges while providing flexibility and adaptability for various applications.So here is another improvised model circuit that will eliminate the unwanted DC offset voltage from the output that affect the previous one discussed. By the way, all previous circuits that I discussed were intended as low power  class d amp source that is adequate to drive head phones via a coupling capacitor.

This means DC offset is ignored due to the added capacitor. The schematic shown below is a reference design with added DC offset adjust pot and a high power fet driver from MICREL but I used it as a power fet substitute to simplify the amplification and cost. With this approach, there`s no need for costly fet driver with level shifter because the PWM source requires same rail supply as with the output fet.

Although chip maker MICREL mentioned that MIC4451 have built-in cross-conduction minimizer, I still provide an option to include it with the use of CD4030 exclusive or gate for added safety. This will also act as phase splitter as required by the two power switchers wired in full bridge topology.

I also assumed that the would be  builder of this circuit understand several subjects like, ringings, RFI, EMI, etc. so adequate power supply by-pass capacitors and short traces of copper tracks must be implemented. Well, building a class d amp from scratch contain lots of challenge and requires courage but for some adventurous hobbyist who are bored with linear, this is worth a try.

The schematic shown above requires minor tweaking on the 555 timer side due to the changes in supply voltage which is at 12 volts now. Here, aside from added offset adjust pot (50% adjust pot via R3), attention must be focused to pin 5 as well because this is the inverting input of the internal comparator which is tied-up from the voltage divider that requires tweaking also.

Adjusting R1 pot will also help to accomplish this. Please refer on the schematic shown below. The sawtooth voltage variations from pin 6 does not conforms to the required 2/3 VCC of the timer but instead, something less than 2/3 of VCC to obtain low distortion. For best result, adding one opamp as a replacement to 2N3904 will give better result. I include LTspice simulation for you to play with. Either R2 or C2 can be adjusted for dead time adjustment to the lowest distortion as possible withoutcrossconduction.

You may disregard this RC delaying network and its ORed diode resistor combination from the output and use it only as phase splitter if you like. Yes, There is a mistake in the drawing. THRS + TRIG must be connected to the center of the pot and not to D1 + R3. Thanks for correcting my mistake. I just corrected the drawing only now.